The instant invention relates to gate control circuits for power MOS transistors operating in the switching mode and applies more particularly to so-called VDMOS transistors (vertical diffused MOS) carried out on a substrate at the same time as vertical bipolar transistors.
The instant invention is based on the analysis of the switching ON operation of a power MOS transistor. This analysis will be explained in relation with a simplified connection drawing of a power MOS transistor (FIG. 1A) and operating curves showing the evolution of the gate voltage at the switching ON (FIG. 1B) and the evolution of the drain/source voltage, V.sub.DS, and of the drain/source current, I.sub.DS, at the switching ON (FIG. 1C).
FIG. 1A shows a power MOS transistor 1 designed to control the current flow through a load L, a supply voltage V.sub.CC (for example 200 volts) being impressed to a terminal of the load L and the other terminal of this load being connected to the drain D of the power MOS transistor 1, the source of which is grounded. The load L is usually an inductive load and a free-wheel diode 2 is shown in parallel with this load. One has also drawn in dotted lines, between the drain and the gate of the MOS transistor, the drain/gate capacitance C.sub.DG and between the gate and the source of the MOS transistor the gate/source capacitance C.sub.GS. A switch S permits to apply a voltage V.sub.DD onto the MOS transistor gate, here an N-channel enhancement transistor, for causing its switching ON.
Referring to the curves of FIGS. 1B and 1C, at the switching ON of the switch S, time t0, the voltage on the gate starts increasing until the time t1 when the threshold control voltage of the MOS transistor gate is reached. At that time, the drain/source current starts increasing until a time t2 when the drain/source current reaches the value of the current in the free-wheel diode. Until that time t2, the voltage V.sub.DS remains high. Between the times t2 and t3, the capacitance C.sub.DG is discharged and the drain/source voltage tends towards a very low value correlated with the ON state resistance, R.sub.ON, of the DMOS transistor. After the time t3, the gate voltage increases to the full level of the gate voltage source V.sub.DD in order to maintain the DMOS transistor in the ON state with a minimum R.sub.ON value. Thus, the gate voltage source supplies energy essentially between the times t1t2 and t2-t3 corresponding to the charge of the capacitance C.sub.GS and to the discharge of the capacitance C.sub.DG. By way of example, for a vertical-type DMOS transistor fed under 200 volts, having a switching ON resistance of 0.18 volt, the total gate charge required is typically 40 nanocoulombs. If the switching is carried out in 100 ns, the peak current to be supplied to the DMOS transistor gate is 400 milliamperes. For some implementations, this current dissipation can be excessive.
Thus, the instant invention is based on this analysis and on the fact that the voltage V.sub.DS on the MOS transistor drain remains substantially higher than V.sub.DD virtually until the time t3, as shown in FIG. 1C.